mirror of
https://github.com/zachjs/sv2v.git
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Zachary Snow
67466eaa60
- module instances with modport bindings are now inlined - support for modports in generate loops - support for generic interfaces - implied modport instance propagation - add error message for interface instances missing port list
33 lines
573 B
Verilog
33 lines
573 B
Verilog
module impl;
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reg [1:0] b_index;
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reg b_clock;
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reg [3:0] b_inp;
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wire b_out;
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initial b_index = 0;
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always @(posedge b_clock)
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b_index <= b_index + 1;
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initial b_inp = 4'b1111;
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always @(posedge b_clock)
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b_inp[b_index] <= b_out;
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assign b_out = ^b_inp;
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initial begin
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b_clock <= 0;
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forever
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#5 b_clock <= ~b_clock;
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end
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initial begin
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$monitor("%b %b %b %b", b_index, b_clock, b_inp, b_out);
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#100;
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$finish;
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end
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endmodule
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module top;
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impl impl();
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endmodule
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