mirror of https://github.com/zachjs/sv2v.git
36 lines
1.6 KiB
Markdown
36 lines
1.6 KiB
Markdown
# relong Tests
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These tests are borrowed from Reid Long's [HDL Examples
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repository](https://bitbucket.org/ReidLong/hdl-examples). That repository was
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intended to provide examples for how the conversions in this project could be
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done. sv2v does not necessarily convert code as demonstrated in the examples.
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Notably, sv2v does not create `generate` blocks when converted vectors with
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multiple packed dimensions, uses `localparam`s rather than macros for `enum`
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conversion, and converts `struct` literals to concatenations, rather than
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multiple statements.
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Each test case (say, "foo") is comprised of the following files:
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1. `foo.sv`: original SystemVerilog
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2. `foo.v`: hand-converted Verilog
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3. `foo_tb.v`: basic testbench exercising the given modules
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The SystemVerilog source file is converted to Verilog using sv2v, and then both
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the converted file and the reference Verilog are simulated using Icarus Verilog.
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This produces VCD files for each which are expected to match exactly, except for
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the timestamp.
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## Modifications
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The following differences exist between the tests in this folder and their
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corresponding versions in the source repository.
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1. The `inline_concat` files were modified to remove a stray trailing semicolon.
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Though some tools allow for stray semicolons, `iverilog` does not.
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2. `array.v` previously had a custom implementation of `$clog2`, which was
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removed.
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3. `cache_request.sv` was modified to include a plain decimal literal to ensure
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coverage beyond the unbased-unsized literals.
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4. The `cache_request2` test is omitted. It was only an example for debugging a
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VCS-specific issue encountered with `cache_request`.
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