mirror of https://github.com/zachjs/sv2v.git
63 lines
2.1 KiB
Haskell
63 lines
2.1 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for `logic`
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-}
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-- Regarding `logic` conversion: The SystemVerilog grammar has the concept of a
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-- `data_declaration`, which seems to cover things much more generally. While
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-- obviously `logic` can appear as module items or ports, they can also be
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-- function arguments, for example.
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-- It seems like logic only becomes reg if it is assigned to in an always block.
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module Convert.Logic (convert) where
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import qualified Data.Set as Set
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import Language.SystemVerilog.AST
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type RegIdents = Set.Set String
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convert :: AST -> AST
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convert descriptions = map convertDescription descriptions
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convertDescription :: Description -> Description
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convertDescription (Module name ports items) =
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Module name ports $ map (convertModuleItem idents) items
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where
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idents = Set.unions $ map getRegIdents items
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convertDescription other = other
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getStmtLHSs :: Stmt -> [LHS]
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getStmtLHSs (Block _ stmts) = concat $ map getStmtLHSs stmts
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getStmtLHSs (Case e cases (Just stmt)) = (getStmtLHSs stmt) ++ (getStmtLHSs $ Case e cases Nothing)
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getStmtLHSs (Case _ cases Nothing) = concat $ map getStmtLHSs $ map snd cases
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getStmtLHSs (BlockingAssignment lhs _) = [lhs]
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getStmtLHSs (NonBlockingAssignment lhs _) = [lhs]
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getStmtLHSs (For _ _ _ stmt) = getStmtLHSs stmt
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getStmtLHSs (If _ s1 s2) = (getStmtLHSs s1) ++ (getStmtLHSs s2)
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getStmtLHSs (Timing _ s) = getStmtLHSs s
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getStmtLHSs (Null) = []
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getLHSIdents :: LHS -> [Identifier]
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getLHSIdents (LHS vx ) = [vx]
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getLHSIdents (LHSBit vx _) = [vx]
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getLHSIdents (LHSRange vx _) = [vx]
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getLHSIdents (LHSConcat lhss) = concat $ map getLHSIdents lhss
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getRegIdents :: ModuleItem -> RegIdents
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getRegIdents (AlwaysC _ stmt) =
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Set.fromList idents
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where
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lhss = getStmtLHSs stmt
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idents = concat $ map getLHSIdents lhss
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getRegIdents _ = Set.empty
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convertModuleItem :: RegIdents -> ModuleItem -> ModuleItem
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convertModuleItem idents (LocalNet (Logic mr) ident val) =
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LocalNet (t mr) ident val
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where
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t = if Set.member ident idents then Reg else Wire
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convertModuleItem _ other = other
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