mirror of https://github.com/zachjs/sv2v.git
22 lines
484 B
Verilog
22 lines
484 B
Verilog
module example(
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input wire [7:0] inp,
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output wire [7:0] out
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);
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assign out = ~inp;
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endmodule
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module top;
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reg [7:0] arr1 [1:0];
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reg [7:0] arr2 [1:0][1:0];
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wire [7:0] out1, out2;
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example e1(arr1[0], out1);
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example e2(arr2[0][0], out2);
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initial begin : blk
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integer i;
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for (i = 0; i < 8; i = i + 1) begin
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#1 arr1[0][i] = (8'hAD >> i) & 1'b1;
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#1 arr2[0][0][i] = (8'h42 >> i) & 1'b1;
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end
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end
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endmodule
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