mirror of https://github.com/zachjs/sv2v.git
38 lines
615 B
Systemverilog
38 lines
615 B
Systemverilog
module example;
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initial $display("example");
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endmodule
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module top;
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wire genblk1;
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wire genblk33;
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(* foo = 1 *) wire genblk01;
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genvar genblk001;
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example genblk0001();
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wire x, y;
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wire o1, o2, o3;
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and genblk00001(o1, x, y);
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not genblk000001(o2, o3, o1);
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parameter genblk0000001 = 1;
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`ifndef REF
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typedef logic genblk00000001;
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`endif
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`define BLK genblk000000001
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if (1) begin
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`ifdef REF
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: `BLK
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reg
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`else
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genblk00000001
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`endif
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x = genblk0000001;
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end
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initial begin
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`BLK.x = 1;
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$display("%b", `BLK.x);
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end
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endmodule
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