mirror of https://github.com/zachjs/sv2v.git
23 lines
381 B
Systemverilog
23 lines
381 B
Systemverilog
`define TEST \
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reg x; \
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begin \
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reg [1:0] x; \
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$display("%0d %b", $bits(x), x); \
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end \
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$display("%0d %b", $bits(x), x);
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module top;
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task t;
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input integer unused;
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`TEST
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endtask
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function f;
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input integer unused;
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`TEST
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endfunction
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initial t(f(0));
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initial begin
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`TEST
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end
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endmodule
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