mirror of https://github.com/zachjs/sv2v.git
64 lines
1.6 KiB
Verilog
64 lines
1.6 KiB
Verilog
module top;
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wire [2:0] a;
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wire [6:0] b;
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wire [17:0] c;
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generate
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if (1) begin : foo
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wire [2:0] a;
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wire [14:0] b;
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wire [17:0] c;
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wire [33:0] d;
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end
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endgenerate
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`define INSPECT_SIZE(expr, size) $display(`"expr -> %0d`", size);
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`define INSPECT_DATA(expr) $display(`"expr -> %b`", expr);
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initial begin
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`INSPECT_SIZE(a, 3);
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`INSPECT_SIZE(a.x, 1);
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`INSPECT_SIZE(a.y, 2);
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`INSPECT_SIZE(b, 7);
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`INSPECT_SIZE(b.x, 3);
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`INSPECT_SIZE(b.y, 4);
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`INSPECT_SIZE(c, 18);
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`INSPECT_SIZE(c.x, 5);
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`INSPECT_SIZE(c.y, 6);
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`INSPECT_SIZE(c.z, 7);
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`INSPECT_SIZE(c.z.x, 3);
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`INSPECT_SIZE(c.z.y, 4);
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`INSPECT_SIZE(foo.a, 3);
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`INSPECT_SIZE(foo.a.x, 1);
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`INSPECT_SIZE(foo.a.y, 2);
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`INSPECT_SIZE(foo.b, 15);
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`INSPECT_SIZE(foo.b.x, 7);
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`INSPECT_SIZE(foo.b.y, 8);
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`INSPECT_SIZE(foo.c, 18);
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`INSPECT_SIZE(foo.c.x, 5);
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`INSPECT_SIZE(foo.c.y, 6);
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`INSPECT_SIZE(foo.c.z, 7);
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`INSPECT_SIZE(foo.c.z.x, 3);
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`INSPECT_SIZE(foo.c.z.y, 4);
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`INSPECT_SIZE(foo.d, 34);
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`INSPECT_SIZE(foo.d.x, 9);
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`INSPECT_SIZE(foo.d.y, 10);
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`INSPECT_SIZE(foo.d.z, 15);
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`INSPECT_SIZE(foo.d.z.x, 7);
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`INSPECT_SIZE(foo.d.z.y, 8);
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`INSPECT_DATA(a);
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`INSPECT_DATA(b);
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`INSPECT_DATA(c);
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`INSPECT_DATA(foo.a);
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`INSPECT_DATA(foo.b);
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`INSPECT_DATA(foo.c);
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`INSPECT_DATA(foo.d);
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end
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endmodule
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