mirror of https://github.com/zachjs/sv2v.git
37 lines
753 B
Verilog
37 lines
753 B
Verilog
module top;
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reg [31:0] data;
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reg p1, p2;
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wire [3:0] out_x;
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wire [3:0] out_y;
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Example example(data, p1, p2, out_x, out_y);
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task exhaust;
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begin
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#1 p1 = 0;
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#1 p2 = 0;
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#1 p1 = 0;
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#1 p2 = 1;
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#1 p1 = 1;
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#1 p2 = 0;
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#1 p1 = 1;
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#1 p2 = 1;
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end
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endtask
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initial begin
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$monitor("%2d %b %b %b %b %b", $time,
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data, p1, p2, out_x, out_y);
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#1 data = 32'ha7107338;
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exhaust;
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#1 data = 32'h8f8259e4;
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exhaust;
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#1 data = 32'h80ad046a;
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exhaust;
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#1 data = 32'hbf93017e;
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exhaust;
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#1 data = 32'he6458a2d;
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exhaust;
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end
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endmodule
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