mirror of https://github.com/zachjs/sv2v.git
21 lines
442 B
Systemverilog
21 lines
442 B
Systemverilog
typedef struct packed {
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logic [3:0] a;
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logic [3:0] b;
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} pair;
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typedef struct packed {
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pair [1:0] x;
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pair [1:0] y;
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} pair_list_pair;
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module Example(data, p1, p2, out_x, out_y);
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input pair_list_pair data;
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input logic p1;
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input logic p2;
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output logic [3:0] out_x;
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output logic [3:0] out_y;
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assign out_x = p2 ? data.x[p1].a : data.x[p1].b;
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assign out_y = p2 ? data.y[p1].a : data.y[p1].b;
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endmodule
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