mirror of https://github.com/zachjs/sv2v.git
34 lines
928 B
Verilog
34 lines
928 B
Verilog
module Tester;
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parameter IN_WIDTH = 0;
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parameter OUT_WIDTH = 0;
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parameter CHUNK_SIZE = 0;
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reg [IN_WIDTH-1:0] i;
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wire [OUT_WIDTH-1:0] l1, l2;
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wire [OUT_WIDTH-1:0] r1, r2;
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Streamer #(IN_WIDTH, OUT_WIDTH, CHUNK_SIZE)
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streamer(i, l1, r1, l2, r2);
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localparam DELAY = 8 * (CHUNK_SIZE + 8 * (OUT_WIDTH + 8 * IN_WIDTH));
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initial #DELAY;
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integer idx;
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initial begin
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for (idx = 0; idx < IN_WIDTH; idx = idx + 1) begin
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i = 1 << idx;
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#1 $display("INW=%0d OUTW=%0d CS=%0d i=%b l1=%b r1=%b l2=%b r2=%b",
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IN_WIDTH, OUT_WIDTH, CHUNK_SIZE, i, l1, r1, l2, r2);
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end
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end
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endmodule
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module top;
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generate
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genvar i, o, c;
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for (i = 1; i <= 8; i = i + 1)
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for (o = 1; o <= 8; o = o + 1)
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for (c = 1; c <= i; c = c + 1)
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Tester #(i, o, c) tester();
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endgenerate
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endmodule
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