mirror of https://github.com/zachjs/sv2v.git
27 lines
814 B
Systemverilog
27 lines
814 B
Systemverilog
module Streamer(i, l1, r1, l2, r2);
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parameter IN_WIDTH = 0;
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parameter OUT_WIDTH = 0;
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parameter CHUNK_SIZE = 0;
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input wire [IN_WIDTH-1:0] i;
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output wire [OUT_WIDTH-1:0] l1;
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output wire [OUT_WIDTH-1:0] r1;
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output reg [OUT_WIDTH-1:0] l2;
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output reg [OUT_WIDTH-1:0] r2;
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if (IN_WIDTH <= OUT_WIDTH) begin
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wire [OUT_WIDTH-1:0] lA = {<<CHUNK_SIZE{i}};
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wire [OUT_WIDTH-1:0] rA = {>>CHUNK_SIZE{i}};
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wire [OUT_WIDTH-1:0] lB;
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wire [OUT_WIDTH-1:0] rB;
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assign lB = {<<CHUNK_SIZE{i}};
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assign rB = {>>CHUNK_SIZE{i}};
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assign l1 = lA == lB ? lA : 'x;
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assign r1 = rA == rB ? rA : 'x;
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end
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if (OUT_WIDTH <= IN_WIDTH) begin
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always @* {<<CHUNK_SIZE{l2}} = i;
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always @* {>>CHUNK_SIZE{r2}} = i;
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end
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endmodule
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