mirror of https://github.com/zachjs/sv2v.git
28 lines
774 B
Systemverilog
28 lines
774 B
Systemverilog
module top;
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localparam BW = 3;
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logic [2:0] test;
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logic [3:0] foo;
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logic [3:0] bar;
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integer x;
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reg [7:0] y;
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initial begin
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test = BW'(0);
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$display(test);
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foo = 2'('1);
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$display(foo);
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bar = $bits(bar)'('1);
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$display(bar);
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x = 1'('1); $display("%b %0d", x, x);
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y = 1'('1); $display("%b %0d", y, y);
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x = 2'('0); $display("%b %0d", x, x);
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y = 2'('0); $display("%b %0d", y, y);
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x = 2'('1); $display("%b %0d", x, x);
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y = 2'('1); $display("%b %0d", y, y);
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x = 2'('x); $display("%b %0d", x, x);
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y = 2'('x); $display("%b %0d", y, y);
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x = 2'('z); $display("%b %0d", x, x);
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y = 2'('z); $display("%b %0d", y, y);
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end
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endmodule
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