mirror of https://github.com/zachjs/sv2v.git
31 lines
723 B
Verilog
31 lines
723 B
Verilog
module check;
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wire y;
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if (1) begin : over
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wire [3:0] x;
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assign x[0] = 0;
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initial $display("intf x %b", x);
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end
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if (1) begin : m
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assign over.x[1] = 1;
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initial $display("mod i.x %b", over.x);
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end
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assign over.x[2] = 1'bz;
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initial $display("check over.x %b", over.x);
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initial $display("check y %b", y);
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endmodule
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module top;
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check c();
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if (1) begin : over
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wire [3:0] x;
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assign x[0] = 0;
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initial $display("intf x %b", x);
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end
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if (1) begin : m
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assign over.x[1] = 1;
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initial $display("mod i.x %b", over.x);
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end
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assign over.x[2] = 1'bz;
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initial $display("top over.x %b", over.x);
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endmodule
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