mirror of https://github.com/zachjs/sv2v.git
52 lines
1.0 KiB
Systemverilog
52 lines
1.0 KiB
Systemverilog
module M(x, y);
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parameter P = 0;
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localparam L = 10;
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function automatic integer F;
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input integer inp;
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return inp + L;
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endfunction
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input wire integer x = F(P); // defining a default here is non-standard
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input wire integer y;
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initial #1 $display("M %0d %0d", x, y);
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endmodule
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module N #(
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parameter type P,
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parameter type Q = integer,
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localparam L = 10
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) (
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input wire P x = $bits(P) + L,
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input wire Q y = $bits(Q) + L
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);
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initial #1 $display("N %b %b", x, y);
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endmodule
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interface I #(
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parameter type P,
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parameter type Q = integer,
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localparam L = 10
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) (
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input wire P x = $bits(P) + L,
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input wire Q y = $bits(Q) + L
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);
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initial #2 $display("I %b %b", x, y);
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endinterface
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module top;
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M m0(0, 0);
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M m1(.y(1));
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M#(1) m2(.y(2));
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N#(logic) n0();
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N#(logic) n1(1'b0);
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N#(logic) n2(.y(2));
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N#(byte) n3();
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N#(byte, shortint) n4();
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I#(logic) i0();
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I#(logic) i1(0);
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I#(logic) i2(.y(2));
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I#(byte) i3();
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I#(byte, shortint) i4();
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endmodule
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