mirror of https://github.com/zachjs/sv2v.git
32 lines
733 B
Systemverilog
32 lines
733 B
Systemverilog
module top;
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parameter PARAM = 1;
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`define BASE(expr, full, x, y, z) \
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$display(`"%b %0d %0d %0d expr`", \
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full, x, y, z)
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`ifndef TEST
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typedef byte T;
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typedef struct packed {
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byte x;
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T y;
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integer z;
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} S;
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`define TEST(a, b, c, expr) \
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if (PARAM) begin \
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S s; \
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assign s = expr; \
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initial `BASE(expr, s, s.x, s.y, s.z); \
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end
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`endif
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`TEST(1, 2, 3, '{ x: 1, y: 2, z: 3 })
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`TEST(2, 2, 3, '{ byte: 2, integer: 3 })
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`TEST(3, 3, 2, '{ integer: 2, byte: 3 })
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`TEST(4, 4, 2, '{ integer: 2, T: 4 })
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`TEST(5, 5, 2, '{ integer: 2, T: 4, byte: 5 })
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`TEST(5, 5, 2, '{ 2: 2, byte: 5 })
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`TEST(7, 8, 9, '{ 1: 8, 2: 9, 0: 7 })
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endmodule
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