mirror of https://github.com/zachjs/sv2v.git
16 lines
453 B
Verilog
16 lines
453 B
Verilog
module top;
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parameter [95:0] W = {32'd3, 32'd5, 32'd7};
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localparam Z = W[95:64];
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localparam Y = W[31:0];
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initial $display(W, W[95:64], W[63:32], W[31:0], Z, Y);
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reg [55:0] a, b, c;
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initial begin
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a = {8'd2, 16'd1, 32'd3};
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b = {8'd1, 16'd3, 32'd3};
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c = {8'd4, 16'hFFFF, 32'd4};
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`define DUMP(v) $display("%b %b %b", v[55:48], v[47:32], v[31:0]);
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`DUMP(a) `DUMP(b) `DUMP(c)
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end
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endmodule
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