mirror of https://github.com/zachjs/sv2v.git
81 lines
2.3 KiB
Systemverilog
81 lines
2.3 KiB
Systemverilog
module test;
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typedef struct packed {
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int w, x;
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byte y;
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logic z;
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} struct_a;
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struct_a a;
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wire signed [31:0] a_w, a_x;
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wire signed [7:0] a_y;
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assign a_w = a.w;
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assign a_x = a.x;
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assign a_y = a.y;
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initial begin
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// TODO: The signed fields should not have to be indirected here, but
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// iverilog does not currently support complex arguments to $monitor.
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$monitor("%2d: %b %b %b %b %b", $time, a, a_w, a_x, a_y, a.z);
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#1 a.w = 0;
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#1 a.x = 0;
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#1 a.y = 0;
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#1 a.z = 0;
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#1 a = '{default: 1};
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#1 a = '{default: 2};
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#1 a = '{default: 3};
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#1 a = '{default: 0};
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#1 a = '{default: -1};
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#1 a = '{default: -2};
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#1 a = '{int: 0, default: 1};
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#1 a = '{byte: 0, default: 1};
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#1 a = '{logic: 0, default: 1};
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#1 a = '{logic: 1, int: 2, byte: 3};
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#1 a = '{logic: 1, int: 2, byte: 3, default: -1};
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#1 a = '{int: 3, byte: 2, default: 0};
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#1 a = '{w: 8, int: 0, default: 1};
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#1 a = '{w: 8, byte: 0, default: 1};
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#1 a = '{w: 8, logic: 0, default: 1};
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#1 a = '{w: 8, logic: 1, int: 2, byte: 3};
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#1 a = '{w: 8, logic: 1, int: 2, byte: 3, default: -1};
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#1 a = '{w: 8, int: 3, byte: 2, default: 0};
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end
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typedef struct packed {
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int x;
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struct_a y;
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logic z;
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} struct_b;
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struct_b b;
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wire signed [31:0] b_x;
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assign b_x = b.x;
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initial begin
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#100;
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// TODO: The signed fields should not have to be indirected here, but
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// iverilog does not currently support complex arguments to $monitor.
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$monitor("%2d: %b %b %b %b", $time, b, b_x, b.y, b.z);
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#1 b.x = 0;
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#1 b.y = 0;
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#1 b.z = 0;
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#1 b = '{default: 1};
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#1 b = '{default: 2};
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#1 b = '{default: 3};
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#1 b = '{default: 0};
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#1 b = '{default: -1};
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#1 b = '{default: -2};
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#1 b = '{int: 0, default: 1};
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#1 b = '{byte: 0, default: 1};
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#1 b = '{logic: 0, default: 1};
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#1 b = '{logic: 1, int: 2, byte: 3};
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#1 b = '{logic: 1, int: 2, byte: 3, default: -1};
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#1 b = '{int: 3, byte: 2, default: 0};
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end
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endmodule
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module top; endmodule
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