mirror of https://github.com/zachjs/sv2v.git
36 lines
936 B
Systemverilog
36 lines
936 B
Systemverilog
typedef integer integer_t;
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typedef shortint shortint_t;
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typedef byte byte_t;
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localparam value_a = 1;
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localparam value_b = 2;
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localparam value_c = 3;
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`define DUMP_V(X) initial $display(`"V: X %b %0d %0d`", X, X, $bits(X));
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`define DUMP_T(X) initial begin : \dump``X \
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localparam X x = '1; \
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$display(`"T: X %0d %b`", $bits(X), x); \
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end
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module mod #(
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localparam integer_t LV1 = value_a, LV2 = value_b,
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parameter type PT1 = logic,
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integer PV1 = 100,
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parameter type(PV1) PV2 = PV1 + value_c,
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parameter type PT2 = byte_t,
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shortint_t PV3 = 4,
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localparam LV3 = 5,
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type LT1 = byte_t, LT2 = shortint_t
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);
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`DUMP_V(LV1) `DUMP_V(LV2) `DUMP_V(LV3)
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`DUMP_T(LT1) `DUMP_T(LT2)
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`DUMP_V(PV1) `DUMP_V(PV2) `DUMP_V(PV3)
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`DUMP_T(PT1) `DUMP_T(PT2)
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endmodule
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module top;
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mod m1();
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mod #(byte, 7, 10, logic [3:0], 5) m2();
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mod #(reg [8:0], 8, 11, integer, 6) m3();
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endmodule
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