mirror of https://github.com/zachjs/sv2v.git
49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
module Example;
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initial
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$monitor("%b %b %b %b %b %b %b %b %b",
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arr1, arr2, arr3,
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arr4, arr5, arr6,
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arr7, arr8, arr9
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);
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typedef logic [2:0] Pack;
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Pack [4:0] arr1;
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Pack [4:0] arr2;
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Pack [4:0] arr3;
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initial begin
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#1; arr1 = 'b100101010100100;
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#1; arr1[0][1] = ~arr1[0][1];
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#1; arr1[4][2] = ~arr1[4][2];
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#1; arr2 = 'b100101000110101;
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#1; arr3 = 'b100100111101010;
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#1; arr3[1] = arr3[2];
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end
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Pack [5:1] arr4;
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Pack [5:1] arr5;
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Pack [5:1] arr6;
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initial begin
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#1; arr4 = 'b100101010100100;
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#1; arr4[1][1] = ~arr4[1][1];
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#1; arr4[5][2] = ~arr4[5][2];
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#1; arr5 = 'b100101000110101;
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#1; arr6 = 'b100100111101010;
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#1; arr6[2] = arr6[3];
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end
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Pack [1:5] arr7;
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Pack [1:5] arr8;
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Pack [1:5] arr9;
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initial begin
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#1; arr7 = 'b100101010100100;
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#1; arr7[1][1] = ~arr7[1][1];
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#1; arr7[5][2] = ~arr7[5][2];
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#1; arr8 = 'b100101000110101;
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#1; arr9 = 'b100100111101010;
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#1; arr9[2] = arr9[3];
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end
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endmodule
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