mirror of https://github.com/zachjs/sv2v.git
23 lines
462 B
Systemverilog
23 lines
462 B
Systemverilog
module example(sel, out);
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parameter W = 8;
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typedef struct packed {
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logic [W/2-1:0] x;
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logic [W/2-1:0] y;
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} line_t;
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line_t [3:0] arr;
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initial begin
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arr[0] = 8'b01000011;
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arr[1] = 8'b00010110;
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arr[2] = 8'b10001111;
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arr[3] = 8'b01100110;
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end
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input logic [1:0] sel;
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output line_t out;
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assign out.x = sel ? arr[sel].x : '0;
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always @* out.y = sel ? arr[sel].y : '0;
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endmodule
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