mirror of https://github.com/zachjs/sv2v.git
28 lines
458 B
Verilog
28 lines
458 B
Verilog
module top;
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reg inp;
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wire out1;
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wire out2;
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wire out3;
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Example m1(inp, out1);
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Example #(0) m2(inp, out2);
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Example #(1) m3(inp, out3);
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task dump;
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$display("%b %b %b %b", inp, out1, out2, out3);
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endtask
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initial begin
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#1 dump();
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inp = 0;
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#1 dump();
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inp = 1;
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#1 dump();
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inp = 1'bx;
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#1 dump();
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inp = 1'bz;
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#1 dump();
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end
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endmodule
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