mirror of https://github.com/zachjs/sv2v.git
22 lines
435 B
Verilog
22 lines
435 B
Verilog
module top;
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task i_x;
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input reg [31:0] i;
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$display("I x(%0d)", i);
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endtask
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reg [31:0] w = 31;
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reg [31:0] y = 42;
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task x;
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input reg [31:0] a, b;
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$display("x('{%0d, %0d})", a, b);
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endtask
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task automatic z;
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input reg [31:0] a, b;
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$display("z('{%0d, %0d})", a, b);
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endtask
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initial begin
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i_x(y);
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x(w, y);
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z(w, y);
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end
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endmodule
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