mirror of https://github.com/zachjs/sv2v.git
17 lines
326 B
Systemverilog
17 lines
326 B
Systemverilog
interface Interface;
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parameter P;
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logic [P - 1:0] x;
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endinterface
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module Module1(Interface i);
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localparam P = i.P;
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initial $display("Module1 P=%0d", P);
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endmodule
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module Module2(Interface i);
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Interface #(i.P) i();
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Module1 m(i);
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endmodule
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module top;
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Interface #(5) i();
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Module2 m(i);
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endmodule
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