mirror of https://github.com/zachjs/sv2v.git
22 lines
416 B
Systemverilog
22 lines
416 B
Systemverilog
interface I;
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logic [3:0] x;
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endinterface
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module A(I i);
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initial $display("A %b", i.x);
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endmodule
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module B #(localparam type I = logic [3:0]) (I i);
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initial $display("B %b", i);
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endmodule
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module top;
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I i();
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if (1) begin : blk
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typedef logic I;
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var I i;
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assign i = 0;
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end
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initial $display("%b %b", i.x, blk.i);
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A a(i);
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B b(i.x);
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assign i.x = 1;
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endmodule
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