mirror of https://github.com/zachjs/sv2v.git
54 lines
1.3 KiB
Systemverilog
54 lines
1.3 KiB
Systemverilog
interface Interface #(num_clients = 0);
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bit [num_clients-1:0] req;
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for (genvar i = 0; i < num_clients; ++i) begin : mps
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modport client_mp (output .client_req(req[i]));
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end
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endinterface
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module ClientAnd (client_ifc, bits);
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parameter WIDTH = 2;
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Interface client_ifc;
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input [WIDTH-1:0] bits;
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assign client_ifc.client_req = &bits;
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endmodule
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module ClientTick #(start = 0, period = 1) (Interface client_ifc, input clock);
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initial client_ifc.client_req = start;
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integer counter;
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initial counter = 0;
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always @(posedge clock) begin
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counter += 1;
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if (counter % period == 0)
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client_ifc.client_req = ~client_ifc.client_req;
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end
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endmodule
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module top;
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logic clock;
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initial begin
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clock = 1;
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forever #1 clock = ~clock;
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end
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parameter N = 8;
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Interface #(.num_clients(N)) intf();
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for (genvar j = 0; j < N - 1; j++) begin : clients
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ClientTick #(j, j + 1) client(
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.clock,
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.client_ifc(intf.mps[j + 1].client_mp)
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);
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end
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ClientAnd #(4) client(
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.bits(intf.req[4:1]),
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.client_ifc(intf.mps[0].client_mp)
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);
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initial begin
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$monitor("%0d %b %b", $time, clock, intf.req);
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#100 $finish(0);
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end
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endmodule
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