mirror of https://github.com/zachjs/sv2v.git
19 lines
439 B
Systemverilog
19 lines
439 B
Systemverilog
interface Interface;
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logic [0:1][0:2] arr;
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endinterface
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module Module(intf);
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Interface intf [3:3][1:2];
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assign intf[3][2].arr[1] = 1;
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assign intf[3][2].arr[0][0] = 0;
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initial $display("2: %b", intf[3][2].arr);
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endmodule
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module top;
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Interface intf [1:1][1:2] ();
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Module mod (intf);
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assign intf[1][1].arr[1] = 6;
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assign intf[1][1].arr[0][0] = 1;
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initial $display("1: %b", intf[1][1].arr);
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endmodule
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