mirror of https://github.com/zachjs/sv2v.git
47 lines
1.2 KiB
Systemverilog
47 lines
1.2 KiB
Systemverilog
function [WIDTH-1:0] incr;
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input [WIDTH-1:0] inp;
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reg carry;
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integer idx;
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begin
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carry = 1;
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idx = 0;
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while (carry) begin
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carry = 0;
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if (inp[idx] === 1'b0)
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inp[idx] = 1'b1;
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else if (inp[idx] === 1'b1)
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inp[idx] = 1'bx;
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else if (inp[idx] === 1'bx)
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inp[idx] = 1'bz;
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else begin
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inp[idx] = 1'b0;
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idx = idx + 1;
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carry = idx < WIDTH;
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end
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end
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incr = inp;
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end
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endfunction
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reg [WIDTH-1:0] a, b, c;
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initial begin : x
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integer i, j, k;
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a = 0; b = 0; c = 0;
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for (i = 0; i < 4**WIDTH; ++i) begin
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for (j = 0; j < 4**WIDTH; ++j) begin
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$display("%b ==? %b = 1'b%b",
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a, b, test_weq(a, b));
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$display("%b !=? %b = 1'b%b",
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a, b, test_wne(a, b));
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for (k = 0; k < 4**WIDTH; ++k) begin
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$display("%b inside {%b, %b} = 1'b%b",
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a, b, c, test_inside(a, b, c));
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c = incr(c);
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end
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b = incr(b);
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end
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a = incr(a);
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end
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end
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