mirror of https://github.com/zachjs/sv2v.git
14 lines
454 B
Systemverilog
14 lines
454 B
Systemverilog
module mod(
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input logic input_a, input_b,
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input logic [1:0] input_c,
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input logic [1:0][2:0] input_d,
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output logic [1:0] output_a, output_b,
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output logic [1:0][2:0] output_c,
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output logic [0:1][2:0] output_d
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);
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and gate_a[1:0] (output_a, input_a, input_c);
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and gate_b[1:0] (output_b, input_a, input_b);
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and gate_c[1:0][2:0] (output_c, input_a, input_d);
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and gate_d[1:0][0:2] (output_d, input_b, input_d);
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endmodule
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