mirror of https://github.com/zachjs/sv2v.git
86 lines
1.9 KiB
Verilog
86 lines
1.9 KiB
Verilog
module top;
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wire [0:31] a;
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generate
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genvar n;
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for (n = 0; n < 32; n = n + 1) begin : gen_filter
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assign a[n] = n & 1;
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wire x;
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assign x = a[n];
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end
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endgenerate
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wire [0:31] b;
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generate
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genvar other_n;
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for (other_n = 0; other_n < 32; other_n = other_n + 1) begin : gen_filter_other
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assign b[other_n] = ~gen_filter[other_n].x;
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end
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endgenerate
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integer i;
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initial begin : foo_1
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for (i = 0; i < 32; i = i + 1)
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$display("1: ", a[i]);
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end
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initial begin : foo_2
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integer i;
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for (i = 0; i < 32; i = i + 1)
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$display("2: ", ~a[i]);
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end
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initial begin : foo_3
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integer i;
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integer j;
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j = 42;
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for (i = 0; i < 32; i = i + 1)
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$display("3: ", ~a[i] + 5, " j=", j);
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end
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initial begin : foo_4
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integer i, j;
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j = 97;
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for (i = 0; i < 32; i = i + 1)
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$display("4: ", ~a[i] + 10, " j=", j);
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end
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integer j, k;
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initial begin
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for (j = 0; j < 4; j++)
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for (k = 0; k < 8; k++)
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$display("5: ", ~a[j * 8 + k] + 11);
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end
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initial begin : foo_6
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integer i;
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for (i = 0; i < 32; i = i + 1)
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$display("6: ", ~a[i]);
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end
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initial begin : foo_7
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integer j, k;
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for (j = 0; j < 4; j++)
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for (k = 0; k < 8; k++)
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$display("7: ", ~a[j * 8 + k] + 11);
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end
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initial begin : foo_8
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integer i;
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for (i = 0; i < 32; i = i + 1)
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$display("8: ", a[i], b[i]);
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end
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wire start;
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assign start = gen_filter[0].x;
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initial $display(start);
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wire [0:31] c;
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generate
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for (n = 0; n < 32; n = n + 1)
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assign c[n] = n & 1;
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for (n = 0; n < 32; n = n + 1) begin end
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endgenerate
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endmodule
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