mirror of https://github.com/zachjs/sv2v.git
48 lines
1.4 KiB
Verilog
48 lines
1.4 KiB
Verilog
module top;
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generate
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if (1) begin : blkA
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localparam X = 2;
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localparam Y = X + 1;
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initial $display("blkA X=%0d Y=%0d", X, Y);
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end
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if (1) begin : blkB
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localparam X = 0;
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localparam Y = X + 1;
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initial $display("blkB X=%0d Y=%0d", X, Y);
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initial begin : blk1
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localparam Y = 100;
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$display("blkB.blk1 X=%0d Y=%0d", X, Y);
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end
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initial begin : blk2
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integer Y;
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Y = 102;
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$display("blkB.blk2 X=%0d Y=%0d", X, Y);
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end
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initial begin : blk3
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reg [7:0] Y;
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$display("blkB.blk3 $bits(X)=%0d $bits(Y)=%0d", $bits(X), $bits(Y));
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end
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if (1) begin : blk4
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genvar X;
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for (X = 0; X < 2; X = X + 1)
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initial $display("blkB.blk4 X=%0d Y=%0d", X, Y);
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end
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if (1) begin : blk5
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wire [3:0] X = 7;
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initial $display("blkB.blk5 X=%0d Y=%0d", X, Y);
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end
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end
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localparam [5:0] X = 22;
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localparam [5:0] Y = X + 1;
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initial $display("X=%b Y=%b", X, Y);
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if (1) begin : blkC
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localparam signed [7:0] X = 1;
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localparam signed [7:0] Y = 2;
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initial $display("blkC X=%b Y=%b", X, Y);
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initial begin : blk1
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$display("blkC.blk1 X=%b Y=%b", X, Y);
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end
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end
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endgenerate
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endmodule
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