mirror of https://github.com/zachjs/sv2v.git
37 lines
908 B
Verilog
37 lines
908 B
Verilog
module top;
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generate
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if (1) begin : i
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function automatic integer f;
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input unused;
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f = 1;
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endfunction
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if (1) begin : blk
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function automatic integer f;
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input unused;
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f = 2;
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endfunction
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end
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end
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function automatic integer f;
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input unused;
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f = 3;
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endfunction
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if (1) begin : blk
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function automatic integer f;
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input unused;
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f = 4;
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endfunction
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end
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endgenerate
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initial begin
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$display(f(0));
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$display(blk.f(0));
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$display(i.f(0));
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$display(i.blk.f(0));
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$display(top.f(0));
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$display(top.blk.f(0));
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$display(top.i.f(0));
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$display(top.i.blk.f(0));
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end
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endmodule
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