mirror of https://github.com/zachjs/sv2v.git
53 lines
1.1 KiB
Systemverilog
53 lines
1.1 KiB
Systemverilog
`define TEST(id, ctrl) \
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always @* #(2 * id) \
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if (a) \
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ctrl if (b) \
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$display("%0d A 1", id); \
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else \
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$display("%0d A 2", id); \
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always @* #(2 * id + 1) \
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if (a) begin \
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ctrl if (b) \
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$display("%0d B 1", id); \
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end else \
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$display("%0d B 2", id);
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`define NOTHING
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`define ATTRIBUTE (* test *)
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`define FOR for (i = 0; i < 1; i = i + 1)
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`define WHILE while (i < 1)
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`define REPEAT repeat (b)
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`define FOREVER forever #10
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`define TIMING #10
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// The other tested constructs are supported in Verilog-2005.
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`ifdef REF
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`define FOREACH repeat ($bits(i))
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`else
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`define FOREACH foreach (i[j])
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`endif
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module top;
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reg a, b;
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integer i;
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`TEST(0, `NOTHING)
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`TEST(1, `ATTRIBUTE)
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`TEST(2, `FOR)
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`TEST(3, `WHILE)
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`TEST(4, `REPEAT)
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`TEST(5, `FOREACH)
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`TEST(6, `FOREVER)
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`TEST(7, `TIMING)
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initial begin
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repeat (2) begin
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#50 a = 0; b = 0;
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#50 a = 0; b = 1;
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#50 a = 1; b = 0;
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#50 a = 1; b = 1;
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end
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$finish(0);
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end
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endmodule
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