mirror of https://github.com/zachjs/sv2v.git
27 lines
692 B
Systemverilog
27 lines
692 B
Systemverilog
package P;
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typedef struct packed { int unsigned a; int unsigned b; } cfg_t;
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localparam cfg_t cfg = '{a: 8, b: 4};
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typedef enum logic [1:0] { S_A, S_B } enum_e;
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endpackage
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class C #(parameter P::cfg_t cfg = P::cfg);
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typedef logic [$clog2(cfg.a) - 1:0] x_t;
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typedef logic [cfg.b - 1:0] y_t;
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typedef struct packed { P::enum_e e; x_t x; y_t y; } s_t;
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endclass
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module child #(
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parameter P::cfg_t cfg = P::cfg,
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parameter type s_t = C#(cfg)::s_t,
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localparam type x_t = C#(cfg)::x_t
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) (
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input s_t ins,
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output x_t out
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);
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always_comb
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unique case (ins.e)
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P::S_A: out = ins.x;
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default: out = '0;
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endcase
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endmodule
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