mirror of https://github.com/zachjs/sv2v.git
32 lines
715 B
Systemverilog
32 lines
715 B
Systemverilog
`define EXPR $unsigned(WIDTH'(ONES))
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`define TEST(size) \
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localparam WIDTH = ONE * size; \
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localparam x = $unsigned(WIDTH'(ONES)); \
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integer y, z; \
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localparam type T = logic [WIDTH-1:0]; \
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y = T'(ones); \
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z = $unsigned(WIDTH'(ones)); \
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$display(`"size: %b %b %b %b`", x, y, z, $unsigned(WIDTH'(ones)));
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module top;
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parameter ONE = 1;
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parameter signed [0:0] ONES = 1'sb1;
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logic signed [0:0] ones;
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initial ones = 1'sb1;
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task t;
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`TEST(6)
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endtask
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function f;
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input integer unused;
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`TEST(7)
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endfunction
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initial t;
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initial begin
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integer a;
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a = f(0);
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end
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initial begin
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`TEST(8)
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end
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endmodule
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