mirror of https://github.com/zachjs/sv2v.git
27 lines
530 B
Systemverilog
27 lines
530 B
Systemverilog
module Example;
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parameter bit P = 0;
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initial $display("Example: %b", P);
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endmodule
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module top;
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Example a();
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Example #(0) b();
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Example #(1) c();
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Example #(2) d();
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Example #(3) e();
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function bit foo;
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input bit inp;
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return inp ^ 1;
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endfunction
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initial begin
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$display("foo(0) = %b", foo(0));
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$display("foo(1) = %b", foo(1));
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$display("foo(2) = %b", foo(2));
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$display("foo(3) = %b", foo(3));
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end
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bit x;
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assign x = 1;
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endmodule
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