mirror of https://github.com/zachjs/sv2v.git
27 lines
518 B
Verilog
27 lines
518 B
Verilog
`include "always_sense.vh"
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module top;
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reg `INPUTS;
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wire `OUTPUTS;
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mod m(`INPUTS, `OUTPUTS);
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initial begin
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$monitor(`INPUTS, `OUTPUTS);
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repeat (2) begin
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#1 inp1 = 0;
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#1 inp2 = 0;
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#1 inp2 = 1;
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#1 inp1 = 1;
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#1 inp2 = 0;
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#1 inp2 = 1;
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#1 inp2 = 0;
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#1 inp1 = 0;
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#1 inp1 = 1;
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#1 inp2 = 1;
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#1 inp1 = 0;
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#1 inp1 = 1;
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end
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end
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endmodule
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