mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 09:28:12 +02:00
Zachary Snow
95c2bc996c
Specifically, support has been added for non-ANSI style port declarations where the port declaration is separate from the corresponding net or variable declaration.
6 lines
168 B
Systemverilog
6 lines
168 B
Systemverilog
// pattern: declarations `output x` and `wire x \[1:0\]` are incompatible due to different unpacked dimensions
|
|
module top(x);
|
|
output x;
|
|
wire x [1:0];
|
|
endmodule
|