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Zachary Snow
95c2bc996c
Specifically, support has been added for non-ANSI style port declarations where the port declaration is separate from the corresponding net or variable declaration.
6 lines
166 B
Systemverilog
6 lines
166 B
Systemverilog
// pattern: declarations `output \[1:0\] x` and `wire x` are incompatible due to different packed dimensions
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module top(x);
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output [1:0] x;
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wire x;
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endmodule
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