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- support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog
5 lines
131 B
Systemverilog
5 lines
131 B
Systemverilog
// pattern: decl_missing_comma\.sv:3:15: Parse error: expected comma or end of declarations
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module top;
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integer a b;
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endmodule
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