Files
sv2v/test/core/stream_unit.v
2021-07-26 13:03:01 -04:00

6 lines
116 B
Verilog

module top;
parameter W = 8;
reg [W - 1:0] x = 8'b1101_0100;
wire [W - 1:0] y = 8'b0010_1011;
endmodule