simplify mod 1 to 0

This commit is contained in:
Zachary Snow 2021-07-26 13:03:01 -04:00
parent 5345a72c9e
commit 17b01b1683
3 changed files with 12 additions and 0 deletions

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@ -84,6 +84,7 @@ simplifyBinOp Mul (Dec 0) _ = toDec 0
simplifyBinOp Mul (Dec 1) e = e
simplifyBinOp Mul _ (Dec 0) = toDec 0
simplifyBinOp Mul e (Dec 1) = e
simplifyBinOp Mod _ (Dec 1) = toDec 0
simplifyBinOp Add e1 (UniOp UniSub e2) = BinOp Sub e1 e2
simplifyBinOp Add (UniOp UniSub e1) e2 = BinOp Sub e2 e1

6
test/core/stream_unit.sv Normal file
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@ -0,0 +1,6 @@
module top;
parameter W = 8;
logic [W - 1:0] x, y;
assign y = {<<{x}};
initial x = 8'b1101_0100;
endmodule

5
test/core/stream_unit.v Normal file
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@ -0,0 +1,5 @@
module top;
parameter W = 8;
reg [W - 1:0] x = 8'b1101_0100;
wire [W - 1:0] y = 8'b0010_1011;
endmodule