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Zachary Snow
d856c59a36
The latest verion of iverilog enforces declaration ordering more strictly. Update a few test cases to match. sv2v still supports out-of-order items on a best-effort basis.
19 lines
455 B
Verilog
19 lines
455 B
Verilog
module top;
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wire [5:0] arr;
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assign arr[0] = 1;
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initial $display("%b", arr);
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parameter YES = 1;
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generate
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if (YES) begin : blk
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wire [11:0] brr;
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assign brr[0] = 1;
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initial $display("%b", brr);
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if (YES) begin : blk2
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wire [19:0] crr;
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assign crr[0] = 1;
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initial $display("%b", crr);
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end
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end
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endgenerate
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endmodule
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