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12 lines
239 B
Systemverilog
12 lines
239 B
Systemverilog
module top;
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wire [31:0] a;
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wire [0:31] b;
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assign a = 'h64ded943, b = 'hb7151d17;
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initial begin
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$display(a[0+:8]);
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$display(a[15-:8]);
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$display(b[0+:8]);
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$display(b[15-:8]);
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end
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endmodule
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