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12 lines
178 B
Systemverilog
12 lines
178 B
Systemverilog
package P;
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typedef logic T;
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typedef logic [1:0] U;
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endpackage
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module top;
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P::T P_T;
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assign P_T = 0;
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initial $display("%b", P_T);
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P::U P_U = 0;
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endmodule
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