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Zachary Snow
d856c59a36
The latest verion of iverilog enforces declaration ordering more strictly. Update a few test cases to match. sv2v still supports out-of-order items on a best-effort basis.
17 lines
424 B
Verilog
17 lines
424 B
Verilog
module evil_mdl (foo);
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localparam evil_pkg_Z = 1;
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localparam evil_pkg_A = evil_pkg_Z;
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localparam evil_pkg_B = evil_pkg_Z;
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output reg [evil_pkg_B-1:0] foo;
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initial foo = evil_pkg_A;
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endmodule
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module top;
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localparam evil_pkg_Z = 1;
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localparam evil_pkg_A = evil_pkg_Z;
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localparam evil_pkg_B = evil_pkg_Z;
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wire [evil_pkg_B-1:0] foo;
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evil_mdl x(foo);
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initial $monitor(foo);
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endmodule
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