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4756f49750
* Remove unneeded begin/end when the loop is a do/while * Dangling else check passes through statement attributes (bug fix) * Dangling else check passes through most control flow structures to reduce unneeded begin/end * Add test case and update changelog --------- Co-authored-by: qcorradi <[email protected]> Co-authored-by: Zachary Snow <[email protected]>
3 lines
40 B
Verilog
3 lines
40 B
Verilog
`define REF
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`include "dangling_else.sv"
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