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23 lines
326 B
Verilog
23 lines
326 B
Verilog
module top;
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wire a;
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reg b;
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reg en;
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initial begin
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en = 1;
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forever #1 en = ~en;
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end
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test m(a, b, en);
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initial begin
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$monitor($time, a, b, en);
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#1; b = 1;
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#1; b = 0;
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#1; b = 0;
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#1; b = 1;
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#1; b = 0;
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$finish;
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end
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endmodule
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