bump iverilog and use explicit named port connections in tests

.github/workflows/main.yaml

@@ -41,7 +41,7 @@ jobs:
           - macOS-11
     needs: build
     env:
-      IVERILOG_REF: 6307057e8db8419b422361973aca0b435eb2bde1
+      IVERILOG_REF: 872ccd32c45cde18855f76d2a87469f7a23612ba
     steps:
       - uses: actions/checkout@v1
       - name: Install Dependencies (macOS)

test/core/always_latch_tb.v

@@ -8,7 +8,7 @@ module top;
         forever #1 en = ~en;
     end
 
-    test m(.a, .b, .en);
+    test m(a, b, en);
 
     initial begin
         $monitor($time, a, b, en);

test/core/interface_generate.v

@@ -39,7 +39,7 @@ module top;
         genvar j;
         for (j = 0; j < N - 1; j = j + 1) begin : clients
             ClientTick #(j, j + 1) client(
-                .clock,
+                .clock(clock),
                 .client_req(intf.req[j + 1])
             );
         end

test/core/logic_struct_select_tb.v

@@ -1,7 +1,7 @@
 module top;
     reg [1:0] sel;
     wire [7:0] out;
-    example e(.sel, .out);
+    example e(sel, out);
     integer i = 0;
     initial
         for (i = 0; i < 10; i = i + 1)