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Zachary Snow
52197df325
This mode reduces the size of test cases that encounter conversion errors or produce incorrect output. The logic developed slowly over the past three years. It is in a state that I find useful when fielding bug reports, but has some room for improvement in terms of constraints and filtering.
22 lines
456 B
Systemverilog
22 lines
456 B
Systemverilog
package P;
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localparam A = 4;
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endpackage
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module top;
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generate
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if (1) generate
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logic [P::A - 1:0] w;
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endgenerate
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endgenerate
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generate
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case (1)
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1: generate
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genvar i;
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for (i = 0; i < 1; i += 1) generate
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assign y = $bits(genblk1.w);
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endgenerate
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endgenerate
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endcase
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endgenerate
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assign z = y;
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endmodule
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