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20 lines
539 B
Systemverilog
20 lines
539 B
Systemverilog
module top;
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wire [3:0][2:0] arr1 [0:1];
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wire [0:1][3:0][2:0] arr2;
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assign arr1[0][0] = 3'b001;
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assign arr1[0][1] = 3'b011;
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assign arr1[0][2] = 3'b100;
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assign arr1[0][3] = 3'b010;
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assign arr1[1][0] = 3'b110;
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assign arr1[1][1] = 3'b100;
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assign arr1[1][2] = 3'b010;
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assign arr1[1][3] = 3'b101;
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assign arr2[0][0] = arr1[0][0];
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assign arr2[0][1] = arr1[0][1];
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assign arr2[0][3:2] = arr1[0][3:2];
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assign arr2[1][0+:2] = arr1[1][0+:2];
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assign arr2[1][3-:2] = arr1[1][3-:2];
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endmodule
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